View X40411S8I-C_6081966.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1 ? fn8116.0 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-352-6832 | intersil (and design) is a registered trademark of intersil americas inc. copyright intersil americas inc. 2005. all rights reserved all other trademarks mentioned are the property of their respective owners. x40410, x40411, x40414, x40415 4kbit eeprom dual voltage monitor with integrated cpu supervisor features ? dual voltage detection and reset assertion ?standard reset threshold settings see selection table on page 2. ?adjust low voltage reset threshold voltages using special programming sequence ?reset signal valid to v cc = 1v ?monitor three voltages or detect power fail ? independent core voltage monitor (v2mon) ? fault detection register ? selectable power-on reset timeout (0.05s, 0.2s, 0.4s, 0.8s) ? selectable watchdog timer interval (25ms, 200ms,1.4s, off) ? low power cmos ?25a typical standby current, watchdog on ?6a typical standby current, watchdog off ? 4kbits of eeprom ?16 byte page write mode ?5ms write cycle time (typical) ? built-in inadvertent write protection ?power-up/power-down protection circuitry ?block lock protect none or 1/2 of eeprom ? 400khz 2-wire interface ? 2.7v to 5.5v power supply operation ? available packages ?8-lead soic, tssop ? monitor voltages: 5v to 0.9v ? memory security ? independent core voltage monitor applications ? communication equipment ?routers, hubs, switches ?disk arrays, network storage ? industrial systems ?process control ?intelligent instrumentation ? computer systems ?computers ?network servers description the x40410/11/14/15 combines power-on reset con- trol, watchdog timer, supply voltage supervision, and secondary voltage supervision, and block lock ? pro- tect serial eeprom in one package. this combination lowers system cost, reduces board space require- ments, and increases reliability. applying voltage to vcc activates the power-on reset circuit which holds reset/re set active for a period of time. this allows the power supply and system oscilla- block diagram v2fail wdo reset reset x40410/14 x40411/15 fault detection register status register eeprom array data register command decode test & control logic power-on, low voltage reset generation v2mon sda scl v cc (v1mon) + - user programmable threshold reset logic + - v trip1 user programmable v trip2 watchdog timer and reset logic v2mon v cc or *x40410/11= v2mon* x40414/15 = v cc data sheet march 28, 2005
2 fn8116.0 march 28, 2005 low v cc detection circuitry prot ects the user?s system from low voltage co nditions, resetting the system when v cc falls below the minimum v trip1 point. reset/re- set is active until v cc returns to proper operating level and stabilizes. a second volt age monitor circuit tracks the unregulated supply to provide a power fail warning or monitors different power supply voltage. three com- mon low voltage combinations are available, however, intersil?s unique circuits allo ws the threshold for either voltage monitor to be reprogrammed to meet special needs or to fine-tune the threshold for applications re- quiring higher precision. the watchdog timer provides an independent protec- tion mechanism for microcontrollers. when the micro- controller fails to restart a timer within a selectable time out interval, the device activates the wdo signal. the user selects the interval from three preset values. once selected, the interval does not change, even after cycling the power. the memory portion of the device is a cmos serial eeprom array with in tersil?s block lo ck protection. the array is internally organized as x 8. the device features a 2-wire interface and software protocol allowing operation on an i 2 c ? bus. the device utilizes intersil?s proprietary direct write ? cell, providing a minimum endurance of 100,000 cycles and a minimum data retention of 100 years. triple voltage monitors *voltage monitor requires v cc to operation. others are independent of v cc . pin configuration device expected system voltages vtrip1(v) vtrip2(v) por (system) x4040/11 -a -b -c 5v; 3v or 3.3v 5v; 3v 3v; 3.3v; 1.8v 2.0?4.75* 4.55?4.65* 4.35?4.45* 2.85?2.95* 1.70?4.75 2.85?2.95 2.55?2.65 1.65?1.75 reset = x40410 reset = x40411 x40414/15 -a -b -c 3v; 3.3v; 1.5v 3v; 1.5v 3v or 3.3v; 1.1 or 1.2v 2.0?4.75* 2.85?2.95* 2.55?2.65* 2.85?2.95* 0.90?3.50* 1.25?1.35* 1.25?1.35* 0.95?1.05* reset = x40414 reset = x40415 sda v cc 3 2 4 1 6 7 5 8 reset /reset v ss v2mon 3 2 4 1 6 7 5 8 scl wdo v2fail reset/reset scl v ss sda v2fail v2mon wdo v cc x40410/14, x40411/15 x40410/14, x40411/15 8-pin soic 8-pin tssop pin description pin name function soic tssop 13v2fail v2 voltage fail output. this open drain output goes low when v2mon is less than v trip2 and goes high when v2mon exceeds v trip2 . there is no power-up reset delay circuitry on this pin. 24v2mon v2 voltage monitor input. when the v2mon input is less than the v trip2 voltage, v2fail goes low. this input can monitor an unregulated power supply with an external resistor divider or can monitor a second power supply with no external components. connect v2mon to v ss or v cc when not used.the v2mon comparator is supplied by v2mon (x40410/11) or by v cc input (x40414/15). 35reset / reset reset output. (x40411/15) this is an active low, open drain output which goes active whenever v cc falls below v trip1 . it will remain active until v cc rises above v trip1 and for the t purst thereafter. reset output. (x40410/14) this is an active high cmos output which goes active whenever v cc falls below v trip1 . it will remain active until v cc rises above v trip1 and for the t purst thereafter. 46v ss ground 57sda serial data. sda is a bidirectional pin used to transfer data into and out of the device. it has an open drain output and may be wire ored with other open drain or open collector outputs. this pin requires a pull up resistor and the input buffer is always active (not gated). watchdog input. a high to low transition on the sda (while scl is toggled from high to low and followed by a stop condition) restarts the watchdog timer. the absence of this transi- tion within the watchdog time out period results in wdo going active. x40410, x40411, x40414, x40415
3 fn8116.0 march 28, 2005 principles of operation power-on reset application of power to the x40410/11/14/15 activates a power-on reset circuit that pulls the reset/reset pins active. this signal provides several benefits. ? it prevents the system microprocessor from starting to operate with insufficient voltage. ? it prevents the processor from operating prior to stabili- zation of the oscillator. ? it allows time for an fpga to download its configura- tion prior to initiali zation of the circuit. ? it prevents communication to the eeprom, greatly reducing the likelihood of data corruption on power-up. when v cc exceeds the device v trip1 threshold value for t purst (selectable) the circuit releases the reset (x40411) and reset (x40410 ) pin allowing the system to begin operation. low voltage v cc (v1 monitoring) during operation, the x40410/11/14/15 monitors the v cc level and asserts reset/reset if supply voltage falls below a preset minimum v trip1 . the reset/reset signal prevents the microprocessor from operating in a power fail or brownout condition. the v1fail signal remains active until the voltage drops below 1v. it also remains active until v cc returns and exceeds v trip1 for t purst . low voltage v2 monitoring the x40410/11/14/15 also monitors a second voltage level and asserts v2fail if the voltage falls below a preset minimum v trip2 . the v2fail signal is either ored with reset to prevent the microprocessor from operating in a power fail or brownout condition or used to interrupt the microprocessor with notification of an impending power failure. for the x40410/11 the v2fail signal remains active until the v cc drops below 1v (v cc falling). it also remains ac tive until v2mon returns and exceeds v trip2 by 0.2v. this voltage sense circuitry monitors the power supply connected to the v2mon pin. if v cc = 0, v2mon can still be monitored. for the x40414/15 devices, the v2fail signal remains actice until v cc drops below 1vx and remains active until v2mon returns and exceeds v trip2 . this sense circuitry is powered by v cc . if v cc = 0, v2mon cannot be monitored. figure 1. two uses of multiple voltage monitoring 68scl serial clock. the serial clock controls the serial bus timing for data input and output. 71wdo wdo output. wdo is an active low, open drain output which goes active whenever the watch- dog timer goes active. 82v cc supply voltage pin description (continued) pin name function soic tssop 6?10v v cc 5v reg v2mon x40411-a resistors selected so 3v appears on v2mon when unregulated supply reaches 6v. unreg. supply v cc x40414-c reset v2fail system v cc reset reset v2fail v cc system reset notice: no external components requi red to monitor two voltages. 1m 1m v2mon 3.3v reg 1.2v reg v2mon (2.9v) x40410, x40411, x40414, x40415
4 fn8116.0 march 28, 2005 figure 2. v tripx set/reset conditions watchdog timer the watchdog timer circuit monitors the microprocessor activity by monitoring the sda and scl pins. the micro- processor must toggle the sda pin high to low period- ically, while scl also toggle s from high to low (this is a start bit) followed by a stop condition prior to the expira- tion of the watchdog time out period to prevent a wdo signal going active. the state of two nonvolatile control bits in the status register determines the watchdog timer period. the microprocessor can change these watchdog bits by writing to the x40410/11/14/15 control register (also refer to page 19). figure 3. watchdog restart v1 and v2 threshold program procedure (optional) the x40410/11/14/15is shipped with standard v1 and v2 threshold (v trip1, v trip2 ) voltages. these values will not change over normal operat ing and storage conditions. howeve r, in applications where the stan- dard thresholds are not exactl y right, or if higher preci- sion is needed in the threshold value, the x40410/11/14/15 trip points may be adjusted. the pro- cedure is described below, and uses the application of a high voltage control signal. setting a v tripx voltage (x = 1, 2) there are two procedures used to set the threshold voltages (v tripx ), depending if the threshold voltage to be stored is higher or lower than the present value. for example, if the present v tripx is 2.9 v and the new v tripx is 3.2 v, the new voltage can be stored directly into the v tripx cell. if however, the new setting is to be lower than the present setting, then it is neces- sary to ?reset? the v tripx voltage before setting the new value. setting a higher v tripx voltage (x = 1, 2) to set a v tripx threshold to a new voltage which is higher than the present thres hold, the user must apply the desired v tripx threshold voltage to the corre- sponding input pin vcc(v1mon), or v2mon. the vcc(v1mon) and v2mon must be tied together dur- ing this sequence. then, a programming voltage (vp) must be applied to the wdo pin before a start con- dition is set up on sda. next, issue on the sda pin the slave address a0h, followed by the byte address 01h for v trip1 and 09h for v trip2 , and a 00h data byte in order to program v tripx . the stop bit following a valid write operation in itiates the programming sequence. pin wdo must then be brought low to complete the operation. note: this operation does not corrupt the memory array. setting a lower v tripx voltage (x = 1, 2) in order to set v tripx to a lower vo ltage than the present value, then v tripx must first be ?reset? accord- ing to the procedure described below. once v tripx has been ?reset?, then v tripx can be set to the desired voltage using the procedure described in ?setting a higher v tripx voltage?. v cc /v2mon v tripx v p t wc a0h 0 7 70 7 0 scl wdo sda (x = 1, 2) 00h scl sda .6s 1.3s timer start x40410, x40411, x40414, x40415
5 fn8116.0 march 28, 2005 resetting the v tripx voltage to reset a v tripx voltage, apply the programming volt- age (vp) to the wdo pin before a start condition is set up on sda. next, issue on the sda pin the slave address a0h followed by the byte address 03h for v trip1 and 0bh for v trip2 , followed by 00h for the data byte in order to reset v tripx . the stop bit fol- lowing a valid write operation initiates the program- ming sequence. pin wdo must then be brought low to complete the operation. after being reset, the value of v tripx becomes a nomi- nal value of 1.7v or lesser. note: this operation does not corrupt the memory array. control register the control register provides the user a mechanism for changing the block lock and watchdog timer settings. the block lock and watchdog timer bits are nonvolatile and do not change when power is removed. the control register is accessed with a special pream- ble in the slave byte (1011) and is located at address 1ffh. it can only be modified by performing a byte write operation directly to the address of the register and only one data byte is allowed for each register write operation. prior to writing to the control register, the wel and rwel bits must be set using a two step process, with the whole sequence requiring 3 steps. see "writing to the control registers" on page 7. the user must issue a stop, after sending this byte to the register, to initiate the nonvolatile cycle that stores wd1, wd0, pup1, pup0, bp1, and bp0. the x40410/11/14/15 will not acknowledge any data bytes written after the first byte is entered. the state of the control register can be read at any time by performing a rand om read at address 01fh, using the special preamble. only one byte is read by each register read operation. the master should sup- ply a stop condition to be consistent with the bus pro- tocol, but a stop is not required to end this operation. rwel: register write en able latch (volatile) the rwel bit must be set to ?1? prior to a write to the control register. figure 4. sample v trip reset circuit 76543 210 pup1 wd1 wd0 bp 0 rwel wel pup0 1 3 2 4 8 7 6 5 soic v trip1 adj. v p reset 4.7k sda scl c adjust run v2fail v trip2 adj. x4041x x40410, x40411, x40414, x40415
6 fn8116.0 march 28, 2005 figure 5. v tripx set/reset sequence (x = 1, 2) wel: write enable latch (volatile) the wel bit controls the access to the memory and to the register during a write operation. this bit is a vola- tile latch that powers up in the low (disabled) state. while the wel bit is low, writes to any address, including any control regi sters will be ignored (no acknowledge will be issued after the data byte). the wel bit is set by writing a ?1? to the wel bit and zeros to the other bits of the control register. once set, wel remains set unt il either it is reset to 0 (by writing a ?0? to the wel bit and zeros to the other bits of the control register ) or until the part powers up again. writes to the wel bit do not cause a high volt- age write cycle, so the device is ready for the next operation immediately af ter the stop condition. v tripx programming apply v cc and voltage decrease v x actual v tripx - desired v tripx done set higher v x sequence error < mde ? | error | < | mde | yes no error > mde + > desired v tripx to v x desired present value v tripx execute no yes execute v tripx reset sequence execute set higher v tripx sequence new v x applied = old v x applied + | error | new v x applied = old v x applied - | error | execute reset v tripx sequence output switches? note: x = 1, 2 let: mde = maximum desired error vx = v cc , vxmon mde + desired value mde ? acceptable error range error = actual - desired x40410, x40411, x40414, x40415
7 fn8116.0 march 28, 2005 bp: block protect bit (nonvolatile) the block protect bit, bp, determines which blocks of the array are write protected. a write to a protected block of memory is ignored . the block protect bits will prevent write operations to half or none of the array. pup1, pup0: power-up bits (nonvolatile) the power-up bits, pup1 and pup0, determine the t purst time delay. the nominal power-up times are shown in the following table. wd1, wd0: watchdog timer bits (nonvolatile) the bits wd1 and wd0 control the period of the watchdog timer. the options are shown below. writing to the co ntrol registers changing any of the nonvolatile bits of the control and trickle registers requir es the following steps: ? write a 02h to the control register to set the write enable latch (wel). this is a volatile operation, so there is no delay after the write. (operation pre- ceded by a start and ended with a stop). ? write a 06h to the control register to set the register write enable latch (rwel) and the wel bit. this is also a volatile cycle. the zeros in the data byte are required. (operation proceeded by a start and ended with a stop). ? write a one byte value to the control register that has all the control bits set to the desired state. the control register can be represented as qxys 001r in binary, where xy are the wd bits, s isthe bp bit and qr are the power-up bits. this operation proceeded by a start and ended with a stop bit. since this is a nonvolatile write cycle it will take up to 10ms to complete. the rwel bit is reset by this cycle and the sequence must be repeated to change the non- volatile bits again. if bit 2 is set to ?1? in this third step ( qxys 011r ) then the rwel bit is set, but the wd1, wd0, pup1, pup0, and bp bits remain unchanged. writing a second byte to the control register is not allowed. doing so aborts the write operation and returns a nack. ? a read operation occurring between any of the previous operations will not interrupt th e register write operation. ? the rwel bit cannot be reset without writing to the nonvolatile control bits in the control register, power cycling the device or attempting a write to a write protected block. to illustrate, a sequ ence of writes to the device con- sisting of [02h, 06h, 02h] will reset all of the nonvola- tile bits in the control register to 0. a sequence of [02h, 06h, 06h] will leave the nonvolatile bits unchanged and the rwel bit remains set. fault detection register the fault detection register (fdr) provides the user the status of what causes the system reset active. the manual reset fail, watch dog timer fail and three low voltage fail bits are volatile. the fdr is accessed with a special preamble in the slave byte (1011) and is located at address 0ffh. it can only be modified by performing a byte write operation directly to the address of the register and only one data byte is allowed for each register write operation. there is no need to set the wel or rwel in the control register to access this fault detection register. bp protected addresses (size) array lock 0 none none 1 100h ? 1ffh (256 bytes) upper half of memory array pup1 pup0 power-on reset delay ( t purst ) 0 0 50ms 0 1 200ms (factory setting) 1 0 400ms 1 1 800ms wd1 wd0 watchdog time out period 0 0 1.4 seconds 0 1 200 milliseconds 1 0 25 milliseconds 1 1 disabled (factory setting) 7 6543210 lv1f lv2f 0 wdf 0 0 0 0 x40410, x40411, x40414, x40415
8 fn8116.0 march 28, 2005 figure 6. valid data changes on the sda bus at power-up, the fault detection register is defaulted to all ?0?. the system needs to initialize this register to all ?1? before the actual monitoring take place. in the event of any one of the monitored sources failed. the corresponding bits in the register will change from a ?1? to a ?0? to indicate the failure. at this moment, the system should perform a read to the register and noted the cause of the reset. after reading the register the system should reset the register back to all ?1? again. the state of the fault detection register can be read at any time by performing a random read at address 0ffh, using the special preamble. the fdr can be read by performing a random read at offh address of the register at any time. only one byte of data is read by the register read operation. wdf, watchdog timer fail bit (volatile) the wdf bit will set to ?0? when the wdo goes active. lv1f, low v cc reset fail bit (volatile) the lv1f bit will be set to ?0? when v cc (v1mon) falls below v trip1 . lv2f, low v2mon reset fail bit (volatile) the lv2f bit will be set to ?0? when v2mon falls below v trip2 . serial interface interface conventions the device supports a bidirectional bus oriented proto- col. the protocol defines any device that sends data onto the bus as a transmitter, and the receiving device as the receiver. the device controlling the transfer is called the master and the device being controlled is called the slave. the master always initiates data transfers, and provides the clock for both transmit and receive operations. therefore, the devices in this fam- ily operate as slaves in all applications. serial clock and data data states on the sda line can change only during scl low. sda state changes during scl high are reserved for indicating start and stop conditions. see figure 6. serial start condition all commands are preceded by the start condition, which is a high to low transition of sda when scl is high. the device continuously monitors the sda and scl lines for the st art condition and will not respond to any command until this condition has been met. see figure 6. serial stop condition all communications must be terminated by a stop condi- tion, which is a low to high transition of sda when scl is high. the stop condition is also used to place the device into the standby power mode after a read sequence. a stop condition can only be issued after the transmitting device has released the bus. (see figure 6). scl sda data stable data change data stable x40410, x40411, x40414, x40415
9 fn8116.0 march 28, 2005 figure 7. valid start and stop conditions serial acknowledge acknowledge is a software convention used to indi- cate successful data transf er. the transmitting device, either master or slave, will release the bus after trans- mitting eight bits. during t he ninth clock cycle, the receiver will pull the sda line low to acknowledge that it received the eight bits of data. see figure 8. the device will respond wit h an acknowledge after recognition of a start condition and if the correct device identifier and select bits are contained in the slave address byte. if a write operation is selected, the device will respond with an acknowledge after the receipt of each subsequent eight bit word. the device will acknowledge all incoming data and address bytes, except for the slave address byte when the device identifier and/or select bits are incorrect. in the read mode, the device will transmit eight bits of data, release the sda line, then monitor the line for an acknowledge. if an acknowledge is detected and no stop condition is generated by the master, the device will continue to transmit data . the device will terminate further data transmissions if an acknowledge is not detected. the master must then issue a stop condition to return the device to standby mode and place the device into a known state. serial write operations byte write for a write operation, the device requires the slave address byte and a word address byte. this gives the master access to any one of the words in the array. after receipt of th e word address byte, the device responds with an acknowledge, and awaits the next eight bits of data. after receiving the 8 bits of the data byte, the device again responds with an acknowledge. the master then terminates the transfer by generating a stop condition, at which time the device begins the internal write cycle to the nonvolatile memory. during this internal write cycle, the device inputs are disabled, so the de vice will not respond to any requests from the master. the sda output is at high impedance. see figure 9. a write to a protected block of memory will suppress the acknowledge bit. figure 8. acknowledge response from receiver scl sda start stop data output from data output from receiver 8 1 9 start acknowledge scl from master x40410, x40411, x40414, x40415
10 fn8116.0 march 28, 2005 figure 9. byte write sequence page write the device is capable of a page write operation. it is initiated in the same manner as the byte write opera- tion; but instead of terminating the write cycle after the first data byte is transfer red, the master can transmit an unlimited number of 8-bit bytes. after the receipt of each byte, the device will respond with an acknowl- edge, and the address is internally incremented by one. the page address remains constant. when the counter reaches the end of the page, it ?rolls over? and goes back to ?0? on the same page. this means that the master can write 16 bytes to the page starting at any location on that page. if the master begins writing at location 10, and loads 12 bytes, then the first 6 bytes are written to locations 10 through 15, and the last 6 bytes are written to locations 0 through 5. afterwards, the address counter would point to location 6 of the page that was just wr itten. if the master sup- plies more than 16 bytes of data, then new data over- writes the previous data, one byte at a time. figure 10. page write operation figure 11. writing 12 bytes to a 16-byte page starting at location 10. the master terminates the data byte loading by issuing a stop condition, which causes the device to begin the nonvolatile write cycle. as wi th the byte write operation, all inputs are disabl ed until completion of the internal write cycle. see figure 10 for the address, acknowl- edge, and data transfer sequence. s t a r t s t o p slave address byte address data a c k a c k a c k sda bus signals from the slave signals from the master 0 s t a r t s t o p slave address byte address data (n) a c k a c k a c k sda bus signals from the slave signals from the master 0 data (1) a c k (1 n 16) 1010 0 0 address address 10 5 bytes n-1 7 bytes address = 6 address pointer ends here addr = 7 x40410, x40411, x40414, x40415
11 fn8116.0 march 28, 2005 stops and write modes stop conditions that terminate write operations must be sent by the master after sending at least 1 full data byte plus the subsequent ack signal. if a stop is issued in the middle of a data byte, or before 1 full data byte plus its associated ack is sent, then the device will reset itself withou t performing the write. the contents of the arra y will not be effected. acknowledge polling the disabling of the inputs during high voltage cycles can be used to take advantage of the typical 5ms write cycle time. once the stop condition is issued to indi- cate the end of the master?s byte load operation, the device initiates the inte rnal high voltage cycle. acknowledge polling can be initiated immediately. to do this, the master issues a start condition followed by the slave address byte for a write or read operation. if the device is still busy with the high voltage cycle then no ack will be returned. if the device has completed the write operation, an ack will be returned and the host can then proceed with the read or write operation. see figure 12. serial read operations read operations are initiated in the same manner as write operations with the exception that the r/w bit of the slave address byte is set to one. there are three basic read operations: current address reads, ran- dom reads, and sequential reads. current address read internally the device contains an address counter that maintains the address of the last word read incre- mented by one. therefore, if the last read was to address n, the next read operation would access data from address n+1. on power-up, the address of the address counter is undefined, requiring a read or write operation for initialization. upon receipt of the slave address byte with the r/w bit set to one, the device issues an acknowledge and then transmits the eight bits of the data byte. the master terminates the read operation when it does not respond with an acknowledge during the ninth clock and then issues a stop condition. see figure 13 for the address, acknowledge, and data transfer sequence. figure 12. acknowledge polling sequence it should be noted that the ninth clock cycle of the read operation is not a ?don?t care.? to terminate a read operation, the master must either issue a stop condi- tion during the ninth cycle or hold sda high during the ninth clock cycle and th en issue a stop condition. random read random read operation allows the master to access any memory location in the array. prior to issuing the slave address byte with the r/w bit set to one, the master must first perform a ?dummy? write operation. the master issues the start condition and the slave address byte, receives an acknowledge, then issues the word address bytes. after acknowledging receipts of the word address bytes, the master immediately issues another start con- dition and the slave address byte with the r/w bit set to one. this is followed by an acknowledge from the device and then by the eight bit word. the master terminates the read operation by not responding with an acknowledge and then issuing a stop condition. see figure 14 for the address, acknowledge, and data transfer sequence. ack returned? issue slave address byte (read or write) byte load completed by issuing stop. enter ack polling issue stop issue start no yes high voltage cycle complete. continue command sequence? issue stop no continue normal read or write command sequence proceed yes x40410, x40411, x40414, x40415
12 fn8116.0 march 28, 2005 a similar operation called ?set current address? where the device will perform this op eration if a stop is issued instead of the second start shown in figure 15. the device will go into standby mo de after the stop and all bus activity will be ignored until a start is detected. this operation loads the new address into the address counter. the next current address read operation will read from the newly loaded address. this operation could be useful if the master knows the next address it needs to read, but is not ready for the data. sequential read sequential reads can be initiated as either a current address read or random address read. the first data byte is transmitted as with the other modes; however, the master now responds wi th an acknowledge, indicat- ing it requires additional dat a. the device continues to output data for each acknow ledge received. the master terminates the read operation by not responding with an acknowledge and then issu ing a stop condition. the data output is sequential, with the data from address n followed by the data from address n + 1. the address counter for read operations increments through all page and column addresses, allowing the entire memory contents to be serially read during one opera- tion. at the end of the addr ess space the counter ?rolls over? to address 0000 h and the device continues to out- put data for each acknowl edge received. see figure 15 for the acknowledge and data transfer sequence. serial device addressing memory address map cr, control register, cr7: cr0 address: 1ff hex fdr, fault detectionr egister, fdr7: fdr0 address: 0ff hex general purpose memory organization, a8:a0 address: 00h to 1ffh general purpose memory array configuration slave address byte following a start condition, the master must output a slave address byte. this byte consists of several parts: ? a device type identifier th at is always ?101x?. where x=0 is for array, x=1 is for control register or fault detection register. ? next two bits are ?0?. ? next bit that becomes the msb of the address. figure 13. x40410/11 addressing figure 14. current address read sequence memory address a8:a0 000h 0ffh 100h 1ffh lower 256 bytes upper 256 bytes block protect option general purpose memory control register fault detection register 1 1 0 0 1 1 0 1 a8 r/w word address slave byte 1 0 1011 0 0 0 0 0 0 r/w r/w general purpose memory control register fault detection register a7 1 a6 a5 a4 a1 a0 1 a3 a2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 s t a r t s t o p slave address data sda bus signals from the slave signals from the master 1 1010 0 0 x40410, x40411, x40414, x40415
13 fn8116.0 march 28, 2005 figure 15. random address read sequence ? one bit of the slave command byte is a r/w bit. the r/w bit of the slave address byte defines the oper- ation to be performed. when the r/w bit is a one, then a read operation is selected. a zero selects a write operation. word address the word address is either supplied by the master or obtained from an internal counter. the internal counter is undefined on a power-up condition. operational notes the device powers-up in the following state: ? the device is in the low power standby state. ? the wel bit is set to ?0?. in this state it is not possi- ble to write to the device. ? sda pin is the input mode. ? reset/reset signal is active for t purst . data protection the following circuitry has been included to prevent inadverten t writes: ? the wel bit must be set to allow write operations. ? the proper clock count and bit sequence is required prior to the stop bit in order to start a nonvolatile write cycle. ? a three step sequence is required before writing into the control register to change watchdog timer or block lock settings. figure 16. sequential read sequence 0 slave address byte address a c k a c k s t a r t s t o p slave address data a c k 1 s t a r t sda bus signals from the slave signals from the master 101 0 0 data (2) s t o p slave address data (n) a c k a c k sda bus signals from the slave signals from the master 1 data (n-1) a c k a c k (n is any integer greater than 1) data (1) x40410, x40411, x40414, x40415
14 fn8116.0 march 28, 2005 absolute maximum ratings temperature under bias .................... -65c to +135c storage temperature ......................... -65c to +150c voltage on any pin with respect to v ss ...................................... -1.0v to +7v d.c. output current ............................................... 5ma lead temperature (soldering, 10 seconds)........ 300c comment stresses above those liste d under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only; functional operation of the device (at these or any ot her conditions above those listed in the operational sections of this specification) is not implied. exposure to absolute maximum rating con- ditions for extended periods ma y affect device reliability. recommended operating conditions *see ordering info temperature min. max. commercial 0c 70c industrial -40c +85c version chip supply voltage monitored* voltages x40410/11 -a or -b 2.7v to 5.5v 2.6v to 5v x40410/11- c, x40414/15 2.7v to 5.5v 1v to 3.6v d.c. operating characteristics (over the recommended operating cond itions unless otherwise specified) symbol parameter min. typ. (4) max. unit test conditions i cc1 (1) active supply current ( v cc ) read 1.5 ma v il = v cc x 0.1 v ih = v cc x 0.9, f scl = 400khz i cc2 (1) active supply current ( v cc ) read 3.0 ma i sb1 (1)(6) standby current ( v cc ) ac (wdt off) 6 10 a v il = v cc x 0.1 vih = v cc x 0.9 f scl , f sda = 400khz i sb2 (2)(6) standby current ( v cc ) dc (wdt on) 25 30 a v sda = v scl = v cc others = gnd or v cc i li input leakage current (scl) 10 a v il = gnd to v cc i lo output leakage current (sda, v2fail , wdo , reset ) 10 a v sda = gnd to v cc device is in standby (2) v il (3) input low voltage (sda, scl) -0.5 v cc x 0.3 v v ih (3) input high voltage (sda, scl) v cc x 0.7 v cc + 0.5 v v hys (6) schmitt trigger input hysteresis ? fixed input level ? v cc related level 0.2 .05 x v cc v v v ol output low voltage (sda, re- set/reset , v2fail , wdo ) 0.4 v i ol = 3.0ma (2.7-5.5v) i ol = 1.8ma (2.7-3.6v) v oh output (reset) high voltage v cc - 0.8 v cc - 0.4 vi oh = -1.0ma (2.7-5.5v) i oh = -0.4ma (2.7-3.6v) x40410, x40411, x40414, x40415
15 fn8116.0 march 28, 2005 notes: (1) the device enters the active state after any start, and re mains active until: 9 clock cycl es later if the device selec t bits in the slave address byte are incorrect; 200ns after a stop ending a read operation; or t wc after a stop ending a write operation. (2) the device goes into standby: 200ns after any stop, exc ept those that initiate a high voltage write cycle; t wc after a stop that initiates a high voltage cycle; or 9 clock cycles afte r any start that is not followed by the corre ct device select bits in the slave addre ss byte. (3) v il min. and v ih max. are for reference only and are not tested. (4) at 25c, v cc = 5v. (5) see ordering information for standard programming le vels. for custom programmed levels, contact factory. (6) based on characterization data. equivalent input circuit for vxmon (x = 1, 2) capacitance note: (1) this parameter is not 100% tested. v cc supply v trip1 (5) v cc trip point voltage range 2.0 4.75 v 4.55 4.6 4.65 v x40410/11-a 4.35 4.4 4.45 v x40410/11-b 2.85 2.9 2.95 v x40410/11-c, x40414/15-a&c 2.55 2.6 2.65 v x40414/15-b t rpd2 (6) v trip2 to v2fail 5s second supply monitor i v2 v2mon current 15 a v trip2 v2mon trip point voltage range 1.7 0.9 4.75 3.5 v v x40410/11 x40414/15 2.85 2.9 2.95 v x40410/11-a 2.55 2.6 2.65 v x40410/11-b 1.65 1.7 1.75 v x40410/11-c 1.25 1.3 1.35 v x40414/15-a&b 0.95 1.0 1.05 v x40414/15-c d.c. operating characteristics (continued) (over the recommended operating cond itions unless otherwise specified) symbol parameter min. typ. (4) max. unit test conditions + ? v ref t rpdx = 5s worst case output pin vxmon r c ? v = 100mv ? v v ref symbol parameter max. unit test conditions c out (1) output capacitance (sda, reset, reset , v2fail , wdo ) 8pf v out = 0v c in (1) input capacitance (scl) 6 pf v in = 0v x40410, x40411, x40414, x40415
16 fn8116.0 march 28, 2005 equivalent a.c. output load circuit for v cc = 5v a.c. test conditions symbol table input pulse levels v cc x 0.1 to v cc x 0.9 input rise and fall times 10ns input and output timing levels v cc x 0.5 output load standard output load 5v sda 30pf v2mon 4.6k ? reset 30pf 2.06k ? v2fail v out 4.6k ? 30pf wdo must be steady will be steady may change from low will change from low to high may change from high to low will change from high to low don?t care: changes allowed changing: state not known n/a center line is high impedance waveform inp uts outputs x40410, x40411, x40414, x40415
17 fn8116.0 march 28, 2005 a.c. characteristics note: (1) cb = total capacitance of one bus line in pf. timing diagrams bus timing symbol parameter 400khz unit min. max. f scl scl clock frequency 0 400 khz t in pulse width suppression time at inputs 50 ns t aa scl low to sda data out valid 0.1 0.9 s t buf time the bus free before start of new transmission 1.3 s t low clock low time 1.3 s t high clock high time 0.6 s t su:sta start condition setup time 0.6 s t hd:sta start condition hold time 0.6 s t su:dat data in setup time 100 ns t hd:dat data in hold time 0 s t su:sto stop condition setup time 0.6 s t dh data output hold time 50 ns t r sda and scl rise time 20 +.1cb (1) 300 ns t f sda and scl fall time 20 +.1cb (1) 300 ns cb capacitive load for each bus line 400 pf t su:sto t high t su:sta t hd:sta t hd:dat t su:dat scl sda in sda out t f t low t buf t r t dh t aa x40410, x40411, x40414, x40415
18 fn8116.0 march 28, 2005 write cycle timing nonvolatile write cycle timing note: (1) t wc is the time from a valid stop condition at the end of a writ e sequence to the end of the self-timed internal nonvolatile write cycle. it is the minimum cycle time to be allowed for any nonvolatile write by the user, unless ac knowledge polling is used. power fail timings symbol parameter min. typ. (1) max. unit t wc (1) write cycle time 5 10 ms scl sda t wc 8 th bit of last byte ack stop condition start condition v2mon v2fail or t r t f t rpdx v rvalid v3fail lowline or v cc or v tripx t rpdx t rpdx t rpdl t rpdl t rpdl x = 2, 3 [] [] x40410, x40411, x40414, x40415
19 fn8116.0 march 28, 2005 reset/reset timings low voltage and watchdog timing parameters notes: (1) v cc = 5v at 25c. (2) values based on characterization data only. symbol parameters min. typ. (1) max. unit t rpd1 (2) v trip1 to reset /reset (power-down only) 5 s t rpdx (2) v trip2 to v2fail 5s t purst power-on reset delay: pup1=0, pup0=0 pup1=0, pup0=1 (factory setting) pup1=1, pup0=0 pup1=1, pup0=1 50 200 (2) 400 (2) 800 (2) ms ms ms ms t f v cc, v2mon , fall time 20 mv / s t r v cc, v2mon , rise time 20 mv / s v rvalid reset valid v cc 1v t wdo watchdog timer period: wd1=0, wd0=0 wd1=0, wd0=1 wd1=1, wd0=0 wd1=1, wd0=1 (factory setting) 1.4 (2) 200 (2) 25 off s ms ms t rst1 watchdog reset time out delay wd1=0, wd0=0 wd1=0, wd0=1 100 200 300 ms t rst2 watchdog reset time out delay wd1=1, wd0=0 12.5 25 37.5 ms t rsp watchdog timer restart pulse width 1 s v cc v trip1 reset reset t purst t purst t r t f t rpd1 v rvalid x40410, x40411, x40414, x40415
20 fn8116.0 march 28, 2005 watchdog time out for 2-wire interface v tripx set/reset conditions < t wdo t rst wdo sda start t wdo t rst scl start t rsp wdt restart start sda scl minimum sequence to reset wdt clockin (0 or 1) scl sda v cc /v2mon (v tripx ) wdo t tsu t thd t vph t vps v p t wc t vpo a0h 0 7 70 7 sets v trip1 sets v trip2 01h* 09h* 03h* 0bh* resets v trip2 resets v trip1 0 start * all others reserved 00h x40410, x40411, x40414, x40415
21 fn8116.0 march 28, 2005 v trip1 , v trip2 , programming specifications: v cc = 2.0?5.5v; temperature = 25c parameter description min. max. unit t vps wdo program voltage setup time 10 s t vph wdo program voltage hold time 10 s t tsu v tripx level setup time 10 s t thd v tripx level hold (stable) time 10 s t wc v tripx program cycle 10 ms t vpo program voltage off time before next cycle 1 ms v p programming voltage 15 18 v v tran1 v trip1 set voltage range 2.0 4.75 v v tran2 v trip2 set voltage range ? x40410/11 1.7 4.75 v v tran2a v trip2 set to voltage range ? x40414/15 0.9 3.5 v v tv v tripx set voltage variation after programming (-40 to +85c). -25 +25 mv t vps wdo program voltage setup time 10 s x40410, x40411, x40414, x40415
22 fn8116.0 march 28, 2005 packaging information 0.150 (3.80) 0.158 (4.00) 0.228 (5.80) 0.244 (6.20) 0.014 (0.35) 0.019 (0.49) pin 1 pin 1 index 0.010 (0.25) 0.020 (0.50) 0.050 (1.27) 0.188 (4.78) 0.197 (5.00) 0.004 (0.19) 0.010 (0.25) 0.053 (1.35) 0.069 (1.75) (4x) 7 0.016 (0.410) 0.037 (0.937) 0.0075 (0.19) 0.010 (0.25) 0 - 8 x 45 8-lead plastic, soic, package code s8 note: all dimensions in inches (in parentheses in millimeters) 0.250" 0.050" typical 0.050" typical 0.030" typical 8 places footprint x40410, x40411, x40414, x40415
23 fn8116.0 march 28, 2005 packaging information note: all dimensions in inches (in parentheses in millimeters) 8-lead plastic, tsso p, package code v8 see detail ?a? .031 (.80) .041 (1.05) .169 (4.3) .177 (4.5) .252 (6.4) bsc .025 (.65) bsc .114 (2.9) .122 (3.1) .002 (.05) .006 (.15) .047 (1.20) .0075 (.19) .0118 (.30) 0 ? 8 .010 (.25) .019 (.50) .029 (.75) gage plane seating plane detail a (20x) (4.16) (7.72) (1.78) (0.42) (0.65) all measurements are typical x40410, x40411, x40414, x40415
24 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com fn8116.0 march 28, 2005 ordering information part mark information v cc range v trip1 range v trip2 range package operating temperature range part number with reset part number with reset 2.9-5.5 4.6v50mv 2.9v50mv 8l soic 0 o c - 70 o c x40410s8-a x40411s8-a -40 o c - 85 o c x40410s8i-a x40411s8i-a 8l tssop 0 o c - 70 o c x40410v8-a x40411v8-a -40 o c - 85 o c x40410v8i-a x40411v8i-a 2.6-5.5 4.4v50mv 2.6v50mv 8l soic 0 o c - 70 o c x40410s8-b x40411s8-b -40 o c - 85 o c x40410s8i-b x40411s8i-b 8l tssop 0 o c - 70 o c x40410v8-b x40411v8-b -40 o c - 85 o c x40410v8i-b x40411v8i-b 1.7-3.6 2.9v50mv 1.7v50mv 8l soic 0 o c - 70 o c x40410s8-c x40411s8-c -40 o c - 85 o c x40410s8i-c X40411S8I-C 8l tssop 0 o c - 70 o c x40410v8-c x40411v8-c -40 o c - 85 o c x40410v8i-c x40411v8i-c 1.3-3.6 2.9v50mv 1.3v50mv 8l soic 0 o c - 70 o c x40414s8-a x40415s8-a -40 o c - 85 o c x40414s8i-a x40415s8i-a 8l tssop 0 o c - 70 o c x40414v8-a x40415v8-a -40 o c - 85 o c x40414v8i-a x40415v8i-a 1.3-3.6 2.6v50mv 1.3v50mv 8l soic 0 o c - 70 o c x40414s8-b x40415s8-b -40 o c - 85 o c x40414s8i-b x40415s8i-b 8l tssop 0 o c - 70 o c x40414v8-b x40415v8-b -40 o c - 85 o c x40414v8i-b x40415v8i-b 1.0-3.6 2.9v50mv 1.0v50mv 8l soic 0 o c - 70 o c x40414s8-c x40415s8-c -40 o c - 85 o c x40414s8i-c x40415s8i-c 8l tssop 0 o c - 70 o c x40414v8-c x40415v8-c -40 o c - 85 o c x40414v8i-c x40415v8i-c 8-lead package x4041xx yywwxx i ? industrial 0/1/4/5 package - s/v blank ? commercial ww ? workweek yy ? year a, b, or c x40410, x40411, x40414, x40415

▲Up To Search▲

Price & Availability of X40411S8I-C

	To Download X40411S8I-C Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .